1. Field of Invention
The present invention relates to a driving circuit of a flat panel display, and more particularly, to a timing controller applicable for controlling a pixel level multiplexing display panel, and a timing controller that is provided without changing architectures of a conventional data driving circuit and a scan driving circuit.
2. Description of Related Art
Flat panel displays, such as a liquid crystal display (LCD), have been widely used in recent years. As the progress of the semiconductor technology, the liquid crystal display (LCD) panel has the advantages of low power consumption, being thin and light, high resolution, high color saturation, long life time, and so on, therefore, it has been widely applied in electronic products closely relevant to the daily life, including liquid crystal screens of a laptop or a desktop computer and an LCD TV.
FIG. 1 is a part of a circuit diagram of a conventional LCD panel. The LCD panel comprises a plurality of pixels 10. Each pixel 10 comprises: a thin film transistor (TFT) 100, a data storage capacitor 101 and a pixel capacitor 102, wherein the gate of the TFT 100 is respectively coupled to the corresponding gate lines G1-G5, and the source of the TFT 100 is respectively coupled to the corresponding source line Sn-Sn+7.
FIGS. 2A-2D are driving timings of the conventional LCD panel in the configuration of FIG. 1. In FIGS. 2A-2D, each block P(1,1)˜P(M,N) represents one pixel respectively. The controlling manner of the LCD in such a configuration is to enable each of the gate lines G1˜GM in sequence, wherein when G1 is enabled, the data of P(1,1)˜P(1,N) are sent to the source line of the panel, when G2 is enabled, the data of P(2,1)˜P(2,N) are sent to the source line of the panel, and when GM is enabled, the data of P(m,1)˜P(m,N) are sent to the source line of the panel . . . and so forth, which is finished until the whole picture is displayed. When the horizontal resolution of the panel is N, the display panel at least needs N source lines.
FIG. 3 is a pixel level multiplexing (PLM) display panel. Compared with the conventional art of FIG. 1, the source lines in the panel are one half of that of the conventional LCD panel in FIG. 1. In this panel, two pixels share one source line, and it must be driven by way of time-division multiplexing. Therefore, the conventional timing controller cannot be used in this panel.